The present invention relates to an electronic device, and more particularly, to a technique suitable for use in an electronic device mounted on a mobile communication device.
In recent years, mobile communication devices (for example, cellular phones), which employ a communication system typified by GSM (Global System for Mobile Communications), PCS (Personal Communication System), PDC (Personal Digital Cellular), or CDMA (Code Division Multiple-Access) system, have gained widespread use throughout the world.
In general, such mobile communication devices are each composed of an antenna for emitting and receiving electric waves, a high-frequency power amplifier (power amplification module) for amplifying power-modulated high-frequency signals to supply them to the antenna, a receiver for processing the high-frequency signals received by the antenna, a controller for controlling the above-mentioned elements, and a cell (battery) for supplying a power supply voltage to these elements.
Japanese Unexamined Patent Publication No. 2005-39320 discloses a technique for a semiconductor element including a semiconductor substrate, and transistors formed on the semiconductor substrate for constituting a first-stage amplifier of a first amplification system and a next-stage amplifier of a second amplification system. At a partial area of the semiconductor substrate, there are provided first, second and third transistors constituting the first-stage amplifier of the first amplification system and the next-stage amplifier of the second amplification system, and a switch element for selecting predetermined two of the aforesaid three transistors according to a switching signal input. The switching by the switch element leads to formation of the first-stage amplifier of the first amplification system by means of the second and third transistors, or formation of the next-stage amplifier of the second amplification system by means of the first and second transistors.
Japanese Unexamined Patent Publication No. 2004-128288 discloses a technique which comprises a module substrate with front and back surfaces, and having a cavity part formed on the back surface, a control chip mounted on the front surface of the module substrate, chip components adjacent to the control chip and mounted on the front surface, an output chip disposed within the cavity part on the back surface of the module substrate, a plurality of lands disposed on the back surface of the module substrate, and a seal part for sealing the control chip and the plurality of chip components. A first GND pattern electrically connected to a GND potential is provided on the module substrate for strengthening an electromagnetic shield between the control chip on the front surface and the output chip on the back surface.
Japanese Unexamined Patent Publication No. 2004-296627 discloses a technique in which a source electrode on the back surface of a semiconductor chip with a n-channel LDMOS for amplification formed therein is coupled with a wiring pattern on a main surface of a wiring board. Also, the source electrode is connected electrically and thermally to a wiring pattern for supply of a reference potential on the back surface of the wiring board through a via hole extending from the main surface of the wiring board to the back surface thereof. Furthermore, a drain electrode on the back surface of a semiconductor chip with a pMOS of a trench gate structure formed therein adapted for supplying a power source voltage to the described n-channel LDMOS is coupled with a wiring pattern on the main surface of the wiring board. Also, the drain electrode is connected electrically and thermally to a via hole extending from the main surface of the wiring board to a position at the midpoint of the thickness of the wiring board. Under the via hole, another via hole is provided with an insulating plate sandwiched therebetween.
Japanese Unexamined Patent Publication No. 2003-249868 discloses a technique which comprises chip components including circuit parts having a filter function (a diplexer, and a LPF) laminated on the inner layer of a ceramic multilayer substrate among circuit parts constituting a front end, and a resin multilayer substrate having passive parts laminated on the inner layer thereof among circuit parts having a switch function (RF Switches). The chip components made of the ceramic multilayer substrate, and an active element constituting the switch are integrally mounted on the surface of the resin multilayer substrate. In addition, the chip components made of the ceramic multilayer substrate are mounted in such a state that input/output impedance of each chip component is compatible with the remaining other circuit parts of the front end.